The parameters of the NMOS transistors in the circuit in Figure P10.72 are \(V_{T N}=0.4 \mathrm{~V}, k_{n}^{\prime}=100 \mu \mathrm{A} / \mathrm{V}^{2}, \lambda_{n}=0\) and the parameters of the PMOS transistors in the circuit are \(V_{T P}=-0.6 \mathrm{~V}, k_{p}^{\prime}=40 \mu \mathrm{A} / \mathrm{V}^{2}, \lambda_{p}=0\). Design the circuit such that \(I_{\text {REF }}=50 \mu \mathrm{A}, I_{O 1}=120 \mu \mathrm{A}, I_{D 3}=25 \mu \mathrm{A}\), \(I_{O 2}=150 \mu \mathrm{A}, V_{S D 2}(\mathrm{sat})=0.35 \mathrm{~V}\), and \(V_{D S 5}(\mathrm{sat})=0.35 \mathrm{~V}\).

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REF M www R Figure P10.72 +1.75 V M3 M 102 lov M4 M5 -1.75 V