For the circuit shown in Figure P10.70, (I_{text {REF }}=100 mu mathrm{A}). The transistor parameters are (V_{T

Question:

For the circuit shown in Figure P10.70, $I_{\text {REF }}=100 \mu \mathrm{A}$. The transistor parameters are $V_{T N}=0.4 \mathrm{~V}, V_{T P}=-0.4 \mathrm{~V}, k_{n}^{\prime}=100 \mu \mathrm{A} / \mathrm{V}^{2}, k_{p}^{\prime}=$ $60 \mu \mathrm{A} / \mathrm{V}^{2}$, and $\lambda_{n}=\lambda_{p}=0$. The transistor width-to-length ratios are $(W / L)_{1}=4,(W / L)_{2}=2.5,(W / L)_{3}=6$, and $(W / L)_{4}=4$. Determine $I_{D 2}, I_{O}$, and all gate-to-source voltages.

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