Consider the circuit shown in Figure P10.70. The NMOS transistor parameters are \(V_{T N}=0.4 \mathrm{~V}, k_{n}^{\prime}=100 \mu \mathrm{A} / \mathrm{V}^{2}, \lambda_{n}=0\) and the PMOS transistor parameters are \(V_{T P}=-0.6 \mathrm{~V}, k_{p}^{\prime}=40 \mu \mathrm{A} / \mathrm{V}^{2}, \lambda_{p}=0\). The width-to-length ratios are \((W / L)_{1}=15,(W / L)_{2}=(W / L)_{3}=9\), and \((W / L)_{4}=20\). Assume \(I_{\text {REF }}=200 \mu \mathrm{A}\). Determine \(I_{D 2}, I_{O}\), and \(V_{S D 4}(\) sat).

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'REF V+ MA M3 M M2 Figure P10.70