The transistors in the circuit shown in Figure P10.60 have the same parameters as in Problem 10.60 except for the \((W / L)\) ratios. Design the circuit such that \(I_{O}=50 \mu \mathrm{A}, I_{\mathrm{REF}}=500 \mu \mathrm{A}, V_{D S 2}(\mathrm{sat})=0.5 \mathrm{~V}\), and \(V_{G S 3}=V_{S G 4}\).

Data From Problem 10.60:-

The transistors in the circuit shown in Figure P10.60 have parameters \(V_{T N}=0.4 \mathrm{~V}, \quad V_{T P}=-0.4 \mathrm{~V}, \quad k_{n}^{\prime}=100 \mu \mathrm{A} / \mathrm{V}^{2}, k_{p}^{\prime}=60 \mu \mathrm{A} / \mathrm{V}^{2}\), and \(\lambda_{n}=\lambda_{p}=0\). The transistor width-to-length ratios are \((W / L)_{1}=\) \((W / L)_{2}=20,(W / L)_{3}=5\), and \((W / L)_{4}=10\). Determine \(I_{O}, I_{\mathrm{REF}}\), and \(V_{D S 2}(s a t)\). What are the values of \(V_{G S 1}, V_{G S 3}\), and \(V_{S G 4}\) ?

Transcribed Image Text:

V+ = +3 V IREF MA M3 10 M M2 V-=-3 V Figure P10.60