Assume a five-stage pipeline (instruction fetch, operand fetch, execute, memory, write-back). For the following code show any stalls and indicate where operand forwarding would be needed. 

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ADD R9, R9, R8 MUL R1, R2, R3 LDR R5, (4, R1) SUB R5, R5, R1 ADD R7, R8, R9 MUL R7, R1, R5