Consider the following fragment of assembly language that is to be executed on a generic three way superscalar processor that can accommodate one memory access per clock. Rewrite the code to improve its performance.

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LDR r1, [12] LDR r3, [14] MUL r5, r3, #12 ADD r3, r3, rl STR r3, [14] ADD r1, r1, #4 STR r1, [r2] ADD r7, r7, #14 MUL r7, r1, #5 SUB r6, r6, #4