The following fragment of code is to be executed on two different superscalar processors. The processors have two integer units and two load/store units (i.e., up to two memory accesses and two integer operations can be executed concurrently. The fetch window is eight instructions. Show how it would be executed, cycle-by-cycle, on the following. 

a. Superscalar with in-order issue and in-order execution. 

b. Superscalar with out-of-order issue and out-oforder execution.

Assume that the latency for each instruction is one cycle, except for a load which is two cycles. Assume that the multiply operation has a latency of two cycles and that the multiplier cannot be reused until the previous instruction has been completed.  

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LDR ADD STR ADD ADD LDR ADD ADD ADD STR ADD SUBS r3, [ro] ro, ro, #4 r3, [16] r6, r6, #4 r8, r8, r3 r4, [rl] rl, rl, #4 r4, r4, r3 r4, r4, r4 r4, [12] r2, r2, #4 r5, r5, #1 ;get x[i] ;update pointer ;store q[i] ;update pointer ;keep running total ;get y[i] ;update pointer ;x[i] + y[i] ;2(x[i] + y[i]) ;store z[i] ;update pointer ;dec loop counter