For the following, we consider instruction encoding for instruction set architectures. a. Consider the case of a
Question:
For the following, we consider instruction encoding for instruction set architectures.
a. Consider the case of a processor with an instruction length of 14 bits and with 64 general-purpose registers so the size of the address fields is 6 bits. Is it possible to have instruction encodings for the following?
■ 3 two-address instructions
■ 63 one-address instructions
■ 45 zero-address instructions
b. Assuming the same instruction length and address field sizes as above, determine if it is possible to have
■ 3 two-address instructions
■ 65 one-address instructions
■ 35 zero-address instructions Explain your answer.
c. Assume the same instruction length and address field sizes as above. Further assume there are already 3 two-address and 24 zero-address instructions. What is the maximum number of one-address instructions that can be encoded for this processor?
d. Assume the same instruction length and address field sizes as above. Further assume there are already 3 two-address and 65 zero-address instructions. What is the maximum number of one-address instructions that can be encoded for this processor?
Step by Step Answer:
Computer Architecture A Quantitative Approach
ISBN: 9780128119051
6th Edition
Authors: John L. Hennessy, David A. Patterson