Show how the basic snooping protocol of Figure 5.6 can be changed for a write-through cache. What is the major hardware functionality that is not needed with a write-through cache compared with a write-back cache?

Figure 5.6

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Invalid CPU write Place write miss on bus CPU read Place read miss on bus Exclusive (read/write) CPU read miss Write-back block Place read miss on bus CPU write hit CPU read hit Place invalidate on bus CPU write CPU read hit Shared (read only) CPU write miss Place write miss on bus Cache state transitions based on requests from CPU CPU write miss Write-back cache block Place write miss on bus CPU read miss Place read miss on bus Invalid Write miss for this block Write-back block; abort memory access Exclusive (read/write) Write miss for this block Invalidate for this block memory access Write-back block; abort Read miss for this block Shared (read only) CPU read miss Cache state transitions based on requests from the bus