The circuit in Figure P2.49 consists of four JK flip-flops. Inputs J and K are not shown, because it is assumed that they are both permanently connected to a logical 1. These JK flip-flops are positive edge-triggered (i.e., they change state on the rising edge of the clock). Note that these flip-flops have a CLR ( clear) input that sets Q to 1 when CLR = 1. What does this circuit do? 

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FIGURE P2.49 Clock C Qa CLR Q Reset C Qb CLR Q C Qc CLR Q C Qd CLR Q Cengage Learning 2014