Consider the circuit in Figure P2.50. Assume that all gates are implemented in silicon by NANO gates, NOR gates and inverters. Each NANO gate, NOR gate, or inverter has an internal delay of 0.4 ns. A logic transition at an input may cause a change at the output ( depending on other inputs and the circuit). The time for a transition at the input to appear as a corresponding transition at an output depends on the circuit path and the nature of the gates. What is the longest circuit path through this circuit? What is the worst case delay that a signal experiences going through the circuit? 

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AB A B O D E FIGURE P2.50 G1/ F G3 G2 H G4 G G5 K G7 G6 M N G9 G8 P G