Assuming that the L1 hit time determines the cycle times for P1 and P2, what are their respective clock rates?

In this exercise, we will look at the different ways capacity affects overall performance. In general, cache access time is proportional to capacity. Assume that main memory accesses take 70 ns and that memory accesses are 36% of all instructions. The following table shows data for L1 caches attached to each of two processors, P1 and P2.

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a. b. P1 P2 P1 P2 L1 Size 2 KB 4 KB 16 KB 32 KB L1 Miss Rate 8.0% 6.0% 3.4% 2.9% L1 Hit Time 0.66 ns 0.90 ns 1.08 ns 2.02 ns