The following register transfers are to be executed in the system of Fig. 5-4. For each transfer,
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The following register transfers are to be executed in the system of Fig. 5-4. For each transfer, specify:
(1) The binary value that must be applied to bus select inputs S2, S1, and S0;
(2) The register whose LD control input must be active (if any);
(3) A memory read or write operation (if needed); and
(4) The operation in the adder and logic circuit (if any).
a. AR←PC
b. IR←M[AR]
c. M[AR]←TR
d. AC←DR, DR←AC (done simultaneously)
Fig. 5-4
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