Each of the following VHDL modules contains an error. For brevity, only the architecture is shown; assume that the library use clause and entity declaration are correct. Explain the error and show how to fix it. 

(a) 

(b)

(c)

(d)

(e)

(f)

(g)

architecture synth of latch is begin process(clk) begin if clk ='1' then q