Write a testbench and verify that your design entities from Exercises 7.1–7.3 all work correctly. Which of the four design entities did you find easiest to write and maintain?

Data in Exercises 7.1

Write a VHDL description for a circuit that accepts a four-bit input and outputs true if the input is a Fibonacci number (0, 1, 2, 3, 5, 8, or 13). Your implementation must be done via a case statement.