A synchronous (4-bit) up/down decade counter with output Q works as follows: All state changes occur on the rising edge of the CLK input, except the synchronous clear (CLR). When CLR = 0, the counter is reset regardless of the values of the other inputs. 

If the LOAD input is 0, the data input D is loaded into the counter.
If LOAD = ENT = ENP = UP = 1, the counter is incremented.
If LOAD = ENT = ENP = 1 and UP = 0, the counter is decremented.
If ENT = UP = 1, the carry output (CO) = 1 when the counter is in state 9.
If ENT = 1 and UP = 0, the carry output (CO) = 1 when the counter is in state 0.
(a) Write a Verilog description of the counter.
(b) Draw a block diagram and write a Verilog description of a decimal counter that uses two of the previously specified counters to form a 2-decade decimal up/down counter that counts up from 00 to 99 or down from 99 to 00.
(c) Simulate for the following sequence: load counter with 98, increment three times, do nothing for two clocks, decrement four times, and clear.