(a) What device does the following Verilog code represent?
always @(CLK, Clr, Set)
begin
if(Clr == 1'b1)
Q <= 1'b0;
else if(Set == 1'b1)
Q <= 1'b1;
else if(CLK == 1'b0)
Q <= D;
else begin
end
end
(b) What happens if Clr = Set = 1 in the device in part a?