For the following Verilog code, list the values of B and C at each time a change occurs. Include all deltas and stop your listing when time > 8 ns. Assume that B is changed to 0110 at time 5 ns. Indicate the times at which task P1 is called.
module Q1(B,C);
input[3:0] B;
output[3:0] C;
integer i;
task P1;
input[3:0] A;
output reg[3:0] D;
begin
for(i = 1; i<= 3; i = i+1)

D[i] <= A[i-1];
D[0] <= A[3];
end
endtask
always @(B)
begin
P1(B,C);
#1;
P1(B,C);
end
assign C = B;
endmodule