In the following code, state and nextstate are integers with a range of 0 to 2. always
Question:
In the following code, state and nextstate are integers with a range of 0 to 2.
always @(state,X)
begin
case(state)
0:begin
if(X == 1'b1)
nextstate = 2'b01;
end
1:begin
if(X == 1'b0)
nextstate = 2'b10;
end
2:begin
if(X == 1'b1)
nextstate = 2'b00;
end
endcase
end
(a) Explain why a latch would be created when the code is synthesized.
(b) What signal would appear at the latch output?
(c) Make changes in the case statement that would eliminate the latch.
(d) Can you make changes outside the case statement that would eliminate the latch? If yes, illustrate. If no, explain.
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Related Book For
Digital Systems Design Using Verilog
ISBN: 978-1285051079
1st edition
Authors: Charles Roth, Lizy K. John, Byeong Kil Lee
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