What is wrong with the following model of a 4-to-1 MUX? (It is not a syntax error.)
Question:
What is wrong with the following model of a 4-to-1 MUX? (It is not a syntax error.)
reg [1:0]sel;
always @(A,B,I0,I1,I2,I3)
begin
sel = 0;
if(A == 1'b1)
sel = sel + 1;
else
begin
end
if(B == 1'b1)
sel = sel + 2;
else
begin
end
case(sel)
0:begin
F = I0;
end
1:begin
F = I1;
end
2:begin
F = I2;
end
3:begin
F = I3;
end
endcase
end
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Related Book For
Digital Systems Design Using Verilog
ISBN: 978-1285051079
1st edition
Authors: Charles Roth, Lizy K. John, Byeong Kil Lee
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