Examine the following Verilog code and answer the following questions
module Problem(X,CLK,Z1,Z2);
input X,CLK;
output Z1,Z2;
reg [1:0]State,Nextstate;
initial
begin
State = 2'b00;
Nextstate = 2'b00;
end
always @(State,X)
begin
case(State)
0:begin
if(X == 1'b0)begin
Z1 = 1'b1;
Z2 = 1'b0;
Nextstate = 2'b00;
end
else begin
Z1 = 1'b0;
Z2 = 1'b0;
Nextstate = 2'b01;
end
end
1:begin
if(X == 1'b0)begin
Z1 = 1'b0;
Z2 = 1'b1;
Nextstate = 2'b01;
end
else begin
Z1 = 1'b0;
Z2 = 1'b1;
Nextstate = 2'b10;
end
end
2:begin
if(X == 1'b0)begin
Z1 = 1'b0;
Z2 = 1'b1;
Nextstate = 2'b10;
end
else begin
Z1 = 1'b0;

Z2 = 1'b1;
Nextstate = 2'b11;
end
end
3:begin
if(X == 1'b0)begin
Z1 = 1'b0;
Z2 = 1'b0;
Nextstate = 2'b00;
end
else begin
Z1 = 1'b1;
Z2 = 1'b0;
Nextstate = 2'b01;
end
end
endcase
end
always @(posedge CLK)
begin
State <= Nextstate;
end
endmodule

(a) Draw a block diagram of the circuit implemented by this code.
(b) Write the state table that is implemented by this code.