The following state table is implemented using a ROM and two D flip-flops (falling edge triggered): (a)

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The following state table is implemented using a ROM and two D flip-flops (falling edge triggered):

Q,+Q,* X = 0 X = 1 Q,Q2 X = 0 X = 1 00 01 10 01 10 00 10 00 01 1

(a) Draw the block diagram.
(b) Write Verilog code that describes the system. Assume that the ROM has a delay of 10ns and each flip-flop has a propagation delay of 15ns.

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Digital Systems Design Using Verilog

ISBN: 978-1285051079

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Authors: Charles Roth, Lizy K. John, Byeong Kil Lee

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Question Posted: Jan 08, 2019 12:42 PM

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The following state table is implemented using a ROM and two D flip-flops (falling edge triggered): (a)

Question:

Q,+Q,* X = 0 X = 1 Q,Q2 X = 0 X = 1 00 01 10 01 10 00 10 00 01 1

Step by Step Answer:

a b module ROMQ4X Clk Z input X Clk output reg Z reg 12 Q Qplus reg 20 FSMROM ...View the full answer

Digital Systems Design Using Verilog

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