Design a synchronous, MOD-50 BCD counter by cascading a MOD-10 and a MOD-5 counter together. The MOD-50 counter should have an active-HIGH count enable (enable) and an active-LOW synchronous clear (clrn). Be sure to include the terminal count detection for the one’s digit to cascade with the ten’s digit. Simulate (functional) the counter.

(a) Use LPM_COUNTER. Use any necessary logic gates.

(b) Use an HDL.