Design the constant unit in the pipelined CISC CPU by using the information given in Table 10-4 and multiple-bit multiplexers, AND gates, OR gates, and inverters. Create an HDL model of your design and verify its correctness in simulation.

Table 10-4

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Added or Modified Control Word (Microinstruction) Fields for CISC Register Fields MZ 2b Control Fields CA 8h BS P 2b S See Next See Table Address Table 10-5 10-2 or Constant Action AX, BX R[SA], R[SB] R16 *** R31 DX Source R[DR] and Dest. R[SB] Dest R[DR] with X = 0 R16 *** R31 Code 5h *** zf IM se IM 0x se IMs 10 zf CA 1F 00 OX 10 CS 1F Action Code 2b 00 01 10 11 Action A Data PC 0|| CC Code 2b 00 01 10 LC Action Code Hold CC 0 Load CC 1