Use a computer-based logic minimization program to design the instruction decoder for a RISC from Table 10-3. Create an HDL model of your design and verify its correctness in simulation.

Table 10-3

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Control Words for Instructions Symbolic Notation Action NOP None MOVA R[DR] 1 R[SA] ADD R[DR] SUB AND OR XOR NOT ADI SBI ANI ORI XRI AIU SIU MOVB LSR LSL LD ST JMR SLT BZ BNZ JMP JML R[SA] + R[SB] R[SA] R[SA] ^ R[SB] R[SA] V R[SB] R[SA] R[SB] R[SA] R[SA]+ se IM R[SA] + (se IM)+1 R[SA] ^ zf IM R[DR] R[SA] V zf IM R[DR] R[SA] zf IM R[SA] + z IM R[SA] + (zf IM) + 1 R[DR] R[DR] R[DR] R[DR] R[DR] R[DR] R[DR] R[DR] R[DR] R[DR] R[DR] - 1 1 - - R[SB] - R[SB] + 1 Control Word Values Op Code RW MD BS PS MW FS MBMACS 0000000 0 1000000 1 xx 00 x 00 00 x 0000010 1 00 00 x 0000101 1 00 00 x 0001000 1 00 00 x 0001001 1 00 00 x 00010101 00 00 x 0001011 1 00 00 x 0100010 1 00 00 x 0100101 1 00 00 x 0101000 1 00 00 x 0101001 1 00 00 x 0101010 1 00 00 x 1000010 1 00 00 x 1000101 1 00 00 x 0001100 1 00 00 x 0001101 1 00 00 x 0001110 1 00.00 x 0010000 1 01 00 x 0100000 0 xx 00 x 1110000 0 xx 10 x 1100101 110 00 x xx 01 0 xx 01 1 xx 11 x 00 11 x R[DR] Isr R[SA] by SH R[DR] Isl R[SA] by SH R[DR] M[R[SA]] M[R[SA]] R[SB] PCR[SA] If R[SA] R[SB], then R[DR] = 1 If R[SA] = 0, then PC-PC +1+se IM 1100000 0 If R[SA] = 0, then PC-PC+1+se IM 1001000 0 1101000 0 PC PC + 1 + se IM PC PC +1 + se IM. R[DR] PC+1 0110000 1 0 xxxxXX X X X 0 0000 x 0 x 0 0010 0 0 x 0 0101 0 0 x 0 100000 x 0 1001 0 0 x 0 1010 0 0 x 0 1011 x 0 x 0 0010 1 0 0101 1 0 1000 1 0 0 0 1001 100 0 1010 1 0 0 0 0010 1 0 0 0 0101 1 0 0 0 1100 0 0 1101 x 0 1 0 1 x x 0 x 0 x xXxXX X 0 X 1 xxxxx 0 0 x 0 xXXX X 0 X 0 0101 0 0 x 0 0000 1 0 1 0 0000 1 0 1 0 xxxx 1 x 1 0 0000 1 11 0 1110 x 0