Repeat Problem 10-6 for the instruction SLT R7 R3 R5 with R3 containing 0000F001 and R5 containing 0000000F.

Problem 10-6

For the RISC CPU in Figure 10-8, manually simulate, in hexadecimal, the processing of the instruction ADI R1 R16 2F01 located in PC = 10F.
Assume that R16 contains 0000001F. Show the contents of each of the pipeline platforms and of the register file (the latter only when a change in value occurs) for each of the clock cycles.

Figure 10-8

Transcribed Image Text:

PA PO PC MUX C 0132 BrARAA Adder BrA BS Pas da -BSO Address Instruction memory Instruction IR IM = IR 140 SH = IR 4:0 Instruction decoder RW DA MD SH BS PS MWFS SH -PS Z MA MB AA BA CS Constant unit AA SH FS PC- 1 0 1 0 MA MUXA MUX B Bus A 2* Z+ C+ 32 x 32 Register file with R0 = 0 A data B data-BA MD RW DA A B Modified function unit F Bus B 0 1 2 MUX D Bus D D Data -MB Register file with R0 = 0 IF IF DOF DOF EX Address Data memory Data out MW Data in Write Address Data memory EX WB WB