Compute the output voltage Vo(t) of the circuit shown in Fig. Q2(b) when the input voltage source VCLK (t) is a clock signal with 50% duty cycle defined as = 2 + /8 VCLK (t) = 2 + VCLK (1) n=1,3,5... 1 -os(nnt - n 100 5 mF Fig. Q2(b) -90) + Vo (t)