1. (22 pts) Circle the selected answer for T/F and multiple-choice questions; and fill in the blanks for the rest. Each part is 2 points.

a) T / F A processor can have different CPIs for different programs. b) T / F In multi-cycle implementation the first two stages, instruction fetch and instruction decode, are the same for all instruction classes. c) T / F Increasing the depth of pipelining always decreases performance. d) T / F Pipelining improves the performance by increasing throughput. e) T / F To pass data from an early pipeline stage to a later pipeline stage, the data must be placed in a pipeline register not to lose the data when the next instruction enters that pipeline stage. f) T / F Data forwarding resolves the data hazard that occurs when an instruction tries to read a register following a load instruction that writes the same register. g) The ideal speedup of a pipelined system with four ideal stages is _______________________. h) One solution to data hazards can be ________________________________________________. i) One solution to structural hazards can be ____________________________________________.

j) Which one of the following processors has the highest possible MIPS rate in ideal conditions? a. A single-issue processor driven by a 1 GHz clock. b. A 2-issue processor driven by a 500 MHz clock. c. A 4-issue processor driven by a 250 MHz clock. d. An 8-issue VLIW processor driven by a 200 MHz clock.

k) Which one of the following is NOT calculated by the ALU? a. Arithmetic result for arithmetic instructions b. Memory address for load/store instructions c. Branch target address d. Address of the next instruction