$1.$ Consider switching delays for $10$ fF in a CMOS inverter circuit where n Cox $=98\mathrm{.}3$ AV$2($W$/$L$)$n $=10,($W$/$L$)$p $=20$ VT$,$n $=0\mathrm{.}53$ V Find gate delay of output voltage going down from Vdd by using the average current method. Assume that the input signal is an ideal rectangular pulse switching between $0$ and $1\mathrm{.}2$ V with zero rise$/$fall times. $2.$ Consider a CMOS ring oscillator consisting of an odd number $($n$)$ of identical inverters connected in a ring configuration. The layout of the ring oscillator is such that the interconnection $($wiring$)$ parasitics can be assumed to be zero. Therefore, the delay of each stage is the same, and the average gate delay is called the intrinsic delay as long as identical gates are used. The ring oscillator circuit is often used to quote the circuit speed of a particular technology using the ring oscillator frequency $($f$).$ Show that the stage delay is independent of the transistor sizes, i$.$e$.,$ it remains the same when all the gates are scaled uniformly up or down