1. The following diagram shows a modern chipset and bus architecture for Intel Core i3/i5/i7 processors. Answer the questions below based on the diagram. 4x DDR3-1600 slots PC3-12800 UDIMM ECC/nECC PCle SATA High definition audio 10 External, 4 Internal USB ports: 9x USB 2.0 ECC 1 port with charging function 5x USB 3.0 SI012 Click here to enter text. Click here to enter text. 4th generation Intel Core / Intel Xeon E3-12xx v3 processor (intel Xeon CORE 17 CORE I5 CORE 13 Click here to enter text. DMI 2 Intel C216 PCH (Peripheral Controller Hub) AMT 9 5x SATA 6.0Gbps Ports a) Briefly define the function of the following items in the diagram. Say what the acronym stands for, and write a brief description of its function or purpose. [3 marks] Click here to enter text. PCIe3 x16 Graphics slot What observation or general principle made this possible? [1 mark] Intel HD 4400/4600/P4600 Graphics (on certain CPUs) PCle2 x16 (4) Slot PCle2x4 (1) Slot PCle2 x1 Slot PCIe to PCI Bridge 32-bit PCI Slot Intel I217LM GbE LAN b) In addition to a peripheral controller hub (PCH), previous generations of Intel hardware also had a separate chip that acted as a memory controller hub (MCH). Where is the memory controller functionality located now? Click here to enter text. [1 mark] JU Click here to enter text. 2. The company Cloudflare provides Content Delivery Networks (CDNS) which speed up web sites, particularly when there are many users. CDNs work by hosting multiple copies of a particular web site at small data centres around the world. Suppose Cloudflare's data centres are using a particular brand of network switch which has an MTBF of 3 years. That means it has a 1 in 1095 chance of failing on any particular dax. They want to improve their data centres reliability by adding redundant switches. What does the chance of failure become in a DMR (Dual Modular Redundant) configuration containing two of these network switches? Assume all failures are independent. Show your work and write your answer as "1 in...". [2 marks]