[10 points) A Microprocessor with an Ll and L2 cache, the access times of L1 and L2 caches are 1 and 6 clock cycles respectively. The miss penalty of L2 cache is 20 clock cycles. The miss rate of L1 cache is twice that of L2. The average memory access time of the cache system is 4 cycles. Calculate the miss rates of L1 and L2 caches