10.0 points possible (graded, results hidden Consider the following duration for each stage: IF = 286 ID = 196 EX (addition) = 383 EX (subtraction) = 389 MEM = 182 WB = 332 Now answer the following questions: By how many ns the single cycle datapath clock period is greater than the 5 stage pipeline clock period? Only write the value, no need to mention unit For a single cycle datapath, what is the duration to execute 3 sub instructions, 6 lw instructions and 1 add instruction? If we were to build an architecture where only R type instructions will be executed and design the pipeline according to that, how many clock cycles would be needed to execute consecutive 66 R type instructions (without any dependencies)