11. (5 pts) The shift register in the following figure has a SHIFT/LOAD and CLK in puts. The serial data input (SER) is a 0. The parallel data inputs are D D D D D 0110. If the SHIFT/LOAD signal is shown as follows and the shift register will shift right I bit at each rising edge of the clock, write down the decimal value of the out- put Q at cach clock. For example, at the first clock, it's a load signal. Therefore, the number 6 is loaded into the register, the output is 6 (or 01102) DDDD SHIFTILO - ax 127222 SNETLODI