12.Create the following systems in Verilog and simulate them using testbenches. Include the model code, testbench code and simulation waveform images. You MUST use the wire labels and component labels (module names) as seen in the diagrams below. a. (5 pts.) A Full Adder (FA): Module name FA Outt Icon LUTEEDS inst1 OR2 Out2 OUTPUTDC AND 2 Out3 b. (15 pts.) 3-bit Carry Look Ahead Adder: The inputs and outputs must be 3-bit arrays as seen in the diagrams. i. The carry bit C1: Module name C1 AND Out6 Out5 inst List10 OR XO AND Out4 BLOC inst11 inst ii. The carry bit C2: Module name C2 DO X1 ANO Outz YO Y Out10 Out9 Out8 ANO OR I Out11 Out12 OR Out13 iii. The top-level entity: Module name CLG_Adder qoj Sol FAO FA X[0] Y[oj Cin s ins14 Xu Siu FA1 FA X[11 Y[11 B Cin S Carry1 Cin DNT C1 C1 inst C1 .X201 YO! 02.01 Cin XO YO X120 Y12.01 Yp2.0 Der X2 FA2 FA X[2] A Y[21 B 52 Y12 Carry S S Cin c2 spo. C2 insti AUTPUT SIO2) 012 Cin XO X1 YO Y1 YU inst2 12.Create the following systems in Verilog and simulate them using testbenches. Include the model code, testbench code and simulation waveform images. You MUST use the wire labels and component labels (module names) as seen in the diagrams below. a. (5 pts.) A Full Adder (FA): Module name FA Outt Icon LUTEEDS inst1 OR2 Out2 OUTPUTDC AND 2 Out3 b. (15 pts.) 3-bit Carry Look Ahead Adder: The inputs and outputs must be 3-bit arrays as seen in the diagrams. i. The carry bit C1: Module name C1 AND Out6 Out5 inst List10 OR XO AND Out4 BLOC inst11 inst ii. The carry bit C2: Module name C2 DO X1 ANO Outz YO Y Out10 Out9 Out8 ANO OR I Out11 Out12 OR Out13 iii. The top-level entity: Module name CLG_Adder qoj Sol FAO FA X[0] Y[oj Cin s ins14 Xu Siu FA1 FA X[11 Y[11 B Cin S Carry1 Cin DNT C1 C1 inst C1 .X201 YO! 02.01 Cin XO YO X120 Y12.01 Yp2.0 Der X2 FA2 FA X[2] A Y[21 B 52 Y12 Carry S S Cin c2 spo. C2 insti AUTPUT SIO2) 012 Cin XO X1 YO Y1 YU inst2