4. For 5-stage pipelined processor, mark which stage the processor is in for each instruction. If data forwarding happens, mark it as an arrow from its source to destination. Note that if stalling happens, the affected instruction should remain in the same stage for one more cycle. [10] F: Fetch, D: Decode, E: Execution, M Memory, W: Write 1 23 45 6789 10 u , 0 (Sto) addt 5t2, 50, 8 4. For 5-stage pipelined processor, mark which stage the processor is in for each instruction. If data forwarding happens, mark it as an arrow from its source to destination. Note that if stalling happens, the affected instruction should remain in the same stage for one more cycle. [10] F: Fetch, D: Decode, E: Execution, M Memory, W: Write 1 23 45 6789 10 u , 0 (Sto) addt 5t2, 50, 8