4.14) This exercise is intended to help you understand the relationship between delay slots, control hazards, and branch execution in a pipelines processor. In this exercise, we assume that the following MIPs code is executed on a pipelined processor with a 5-stage pipeline, full forwarding, and a predict- taken branch predictor: lw r2, 0(r1) label1: begr2, ro, label2 not taken once, then taken lw r3, 0(r2) begr3, ro, label1 #taken add r1, r3, r1 label2: sw r1, 0(r2) A) Draw the pipeline execution for this diagram for this code, assuming there are no delay slots and that branches execute in the EX stage B) Repeat A, but assume that delay slots are used. In the given code, the instruction that follows the branch is now the delay slot instruction for that branch. C) One way to move the branch resolution one stage earlier is to not need an ALU operation in conditional branches. The branch instruction would be "bez rd, label" and "bnez rd, label", and it would branch ifthe register has and does not have a zero value, respectively. Change this code to use these branch instructions instead of beg. You can assume that register r* s available for you to use as a temporary register, and that an seg (set if equal) R-type instruction can be used D) Using the first branch instruction in the given code as an example, describe the hazard detection logic needed to support branch execution in the ID stage as in Figure 4.62. Which type of hazard is this new logic supposed to detect? E) For the given code, what is the speedup achieved by moving branch execution into the ID stage? Explain your answer. In your speedup calculation, assume that the additional comparison in the D stage does not affect clock cycle time F) using the rst branch instruction in the given code as an example, describe the forwarding support that must be added to support branch execution in the ID stage. Compare the complexity of this new forwarding unit to the complexity of the existing forwarding unit in Figure 4