5. The figure illustrates the microarchitecture design of datapath and control for a selected set of RISC-V instructions as described in the textbook. As a young computer architect, you are required to add jalr x0, 0(x1) instruction to the existing design. Please note since rd is x0, this instruction is used for procedure return. You do not need to consider update of the destination register (x0). You can use hand drawing to show the additional logic in the dashed area to include the jalr x0, 0(x1) instruction. (Hint: The jalr control signal is generated by the Control logic and sent to the dashed area. Also, the result of the new PC (without jalr) is linked to the dashed area. You need to figure out if any other information is needed. Also with the additional jalr, how you design the logic to update the PC for the next instruction.)

o 2x Add Add Sum Shift left 1 jalr Branch MemRead Instruction (8-01 Memo Rag Control ALUOR Opcode Momo ALUSE RegWrite instruction (19-15) Read register1 Read Instruction (24-20 Read data 1 register 2 tristruction (117) Write Read PC Read address Zero ALU ALU Instruction 31-01 Instruction memory Read Address data result register data 2 x Write data Registers Write Data data memory Instruction (31.01 64 Gen ALU control Instruction (30,14-12 [14-12] func3, [30] func7 for ALU control o 2x Add Add Sum Shift left 1 jalr Branch MemRead Instruction (8-01 Memo Rag Control ALUOR Opcode Momo ALUSE RegWrite instruction (19-15) Read register1 Read Instruction (24-20 Read data 1 register 2 tristruction (117) Write Read PC Read address Zero ALU ALU Instruction 31-01 Instruction memory Read Address data result register data 2 x Write data Registers Write Data data memory Instruction (31.01 64 Gen ALU control Instruction (30,14-12 [14-12] func3, [30] func7 for ALU control