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7.1 In Figure 7.1.3, we showed the design of an SR latch using NOR gates. Replace the NOR gates by NAND gates, S input by

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7.1 In Figure 7.1.3, we showed the design of an SR latch using NOR gates. Replace the NOR gates by NAND gates, S input by X, and R input by Y. Construct the characteristic table of the resulting latch. 0 Figure 7.1.3: An Asynchronous SR Memory Element

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