8. 100 PS 50 ps 80 ps 120 ps (11 points) Assume the latencies for logic blocks are listed in the table below. Please ignore the latency for control signal delay, or other unspecified blocks. Assume only lw instruction is supported. I-memory Registers ALU D-memory IF - DE - EX-WM fo (a) (2 points) For a single-cycle MIPS CPU where the instruction with the longest latency determines the clock cycle time, what's the minimum clock cycle time it can use? (b) (2 points) For a classic MIPS CPU with a 5-stage pipeline, what's the minimum clock cycle time it can use? (c) (2 points) What is the latency of executing lw using the pipelined CPU in (b)? (d) (2 points ) For the CPUs in (a) and (b), what is the speedup of the pipelined CPU versus the single- cycle CPU for executing 100 lw instructions? Assume there is no any data dependency in these instructions. (e) (3 points) Explain why the speedup in (d) in much less than the number of stages in the pipelined CPU