A 10-stage instruction pipeline runs at a clock rate of 1 GHz. The instruction mix is such that 15% of instructions cause one bubble to be inserted into the pipeline, and 10% of instructions cause two bubbles to be inserted. The equivalent single-cycle implementation would lead to a clock rate of 150 MHz.

What is the increase in the pipeline CPI over the ideal CPI as a result of bubbles?

What is the speedup of pipelined implementation over single-cycle?