Consider the following MIPS loop. You should assume the following:

The floating point functional units are pipelined as described in Figures C.34 and C.35; however, floating multiply consists of 5 stages (not 7) and has a latency of 4 (not 6). Note that structural hazards may occur.

Normal MIPS forwarding.

Branch resolved in ID stage.

F0 has been initialized with the value of c.

F4 has been initialized with the value of a.

R1 and R3 have been initialized to refer to the last elements of the x and z arrays, respectively.

C code:

for (i = 100;i > 0;i -- )

z[i] = a*x[i]*x[i]*x[i] + c*x[i];

MIPS loop code:

loop: L.D F6,0(R1)

MUL.D F8,F6,F6

MUL.D F14,F6,F0

MUL.D F10,F8,F6

MUL.D F12,F10,F4

ADD.D F16,F14,F12

DADDUI R1,R1,#-8

S.D F16,0(R3)

DADDUI R3,R3,#-8

BNEZ R1,loop

a. Clearly show via a pipeline diagram one iteration of the loop. You must clearly indicate all stalls.

b. How many clock cycles will it take to execute the loop 10 times?

Latency tion interval Functional unit Integer ALU Data memory (integer and FP loads) FP add FP multiply (also integer multiply) FP divide (also integer divide) 0 24 25 Figure C.34 Latencies and initiation intervals for functional units. EX FP/integer multiply M1 M2 M3 M4 M5 M6 M7 MEM WB FP adder A1A2 A3A4 FP/integer divider Latency tion interval Functional unit Integer ALU Data memory (integer and FP loads) FP add FP multiply (also integer multiply) FP divide (also integer divide) 0 24 25 Figure C.34 Latencies and initiation intervals for functional units. EX FP/integer multiply M1 M2 M3 M4 M5 M6 M7 MEM WB FP adder A1A2 A3A4 FP/integer divider