A $4GHz$ CPU implements a $10-$stage ideal pipeline:

a$)$ What is the machine's bandwidth?

b$)$ What is the average latency of an instruction $($assume ideal pipeline$)?$

c$)$ How long will a program of $1500$ instructions take to run on this CPU?

d$)$ In a cheaper version of the above CPU, and while supporting the same ISA and still running at $4GHz,$ the

manufacturer eliminated the pipeline but implemented a $10-$stage multicycle Datapath. How long will a

program of $1500$ instructions take on this CPU given that it has the following percentages of instructions

with different number of cycles: $6$ cycles: $5\%,7$ cycles: $10\%,8$ cycles: $40\%,9$ cycles: $30\%,10$ cycles: $15\%.$A $4$ GHz CPU implements a $10-$stage ideal pipeline