An engineer tries to use three identical CMOS inverters to implement a quick 3-stage opamp in...
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An engineer tries to use three identical CMOS inverters to implement a quick 3-stage opamp in inverting amplifier configuration, as shown in Fig. 2. Each inverter has gm = 1 mA/V, r. = 20 kg, and an equivalent capacitance C=1pF between its output node and ground. Assume Rz = 2R1 = 200 kg. What is the DC (low-frequency) gain of the opamp? What is the phase margin of the closed loop amplifier Degrees A capacitance Cc is now connected between the output node of I111 and ground to stabilize the circuit. Determine the value of CcCc that results in a phase margin of 70° dB nF Determine the position of the dominant pole in Hz Determine the position of any one of the two non-dominant poles in MHz Determine the value of closed loop bandwidth in MHz +1 mm R₁ www R₂ 12 Figure 2 13 Vo An engineer tries to use three identical CMOS inverters to implement a quick 3-stage opamp in inverting amplifier configuration, as shown in Fig. 2. Each inverter has gm = 1 mA/V, r. = 20 kg, and an equivalent capacitance C=1pF between its output node and ground. Assume Rz = 2R1 = 200 kg. What is the DC (low-frequency) gain of the opamp? What is the phase margin of the closed loop amplifier Degrees A capacitance Cc is now connected between the output node of I111 and ground to stabilize the circuit. Determine the value of CcCc that results in a phase margin of 70° dB nF Determine the position of the dominant pole in Hz Determine the position of any one of the two non-dominant poles in MHz Determine the value of closed loop bandwidth in MHz +1 mm R₁ www R₂ 12 Figure 2 13 Vo
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Related Book For
Analysis and Design of Analog Integrated Circuits
ISBN: 978-0470245996
5th edition
Authors: Paul R. Gray, ? Paul J. Hurst Stephen H. Lewis, ? Robert G. Meyer
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