Assume the following instruction classe stage as shown in the following table. (X indicates that the stage is not being accessed) s and their corresponding distribution with different latencies per IF EX 2ns Distribution 35% 12% 35% 18% MEM 2ns 5ns WB 4ns ID Load Store Arithmetic Branch ns ns 6ns 2ns 4ns a) I4 pointsl Based on the latency in nanoseconds shown in the table, if the architect chose to implement a Single-Cycle Datapath, what is i) the cycle time per instruction and ii) the throughput ("instructions per second") for this program? b) [8 pointsl Now, if the architect implemented a Multi-Cycle Datapath machine, what is i) the cycle time per instruction for this p find ii) the average latency and then the throughput of this program. Is the Multi-cycle datapath faster than the single-cycle datapath for this program? rogram? ? Using the distributions of the instructions in this program c) 12 pointsl Finally, if the architect decided to pipeline this machine into 5 stages, what is the clock cycle and the throughput for this program? (Assuming there is no pipeline stall at all) Assume the following instruction classe stage as shown in the following table. (X indicates that the stage is not being accessed) s and their corresponding distribution with different latencies per IF EX 2ns Distribution 35% 12% 35% 18% MEM 2ns 5ns WB 4ns ID Load Store Arithmetic Branch ns ns 6ns 2ns 4ns a) I4 pointsl Based on the latency in nanoseconds shown in the table, if the architect chose to implement a Single-Cycle Datapath, what is i) the cycle time per instruction and ii) the throughput ("instructions per second") for this program? b) [8 pointsl Now, if the architect implemented a Multi-Cycle Datapath machine, what is i) the cycle time per instruction for this p find ii) the average latency and then the throughput of this program. Is the Multi-cycle datapath faster than the single-cycle datapath for this program? rogram? ? Using the distributions of the instructions in this program c) 12 pointsl Finally, if the architect decided to pipeline this machine into 5 stages, what is the clock cycle and the throughput for this program? (Assuming there is no pipeline stall at all)