Assume the following: The memory is byte addressable. . Memory accesses are to 1-byte words (not to 4-byte words). .. Addresses are 10 bits wide The cache is 2-way associative cache (E-2), with a 8-byte block size (B-8) and 4 sets (S-4) . The following figure shows the format of an address (one bit per box). Indicate (by labeling the diagram) the fields that would be used to determine the following: CO-The cache block offset CI-The cache set index CT-The cache tag 6 4 0 A cache with this configuration could store a total of 1024xbytes of memory (ignoring the tags and valid bits)