Consider the following MIPS design:

a) What is the earliest stage that branches can be resolved in this pipeline? How many instructions are squashed on a taken branch?

b) List all the forwarding paths that are implemented in this figure.

IDIEX IDVEX MemRead ControlMux 0 0 0 Control 4 x4 R1 Adrs Registers Instr RAM Data 2 Result 0 Data RAM F.Flush 0 Forward IDIEX IDVEX MemRead ControlMux 0 0 0 Control 4 x4 R1 Adrs Registers Instr RAM Data 2 Result 0 Data RAM F.Flush 0 Forward