(Correctness) (6 points) Pipeline Forwarding: Princess Peach has provided Mario with a pipelined MIPS processor with the following stages and stage delays: IF = 50ns, ID = 40ns, EX = 35ns, Mem = 60ns, WB = 30ns She has also given Mario the following set of instructions which are to be run on this processor and asked him a few questions. Can you help Mario answer these questions? add $t0, $al, $a0 lw $t1, 1024 ($t0) addi $t0, $50, 141 lw $t2, 4096 ($t0) add $t1, $t2, $t0 C What is the speedup of the given 5 stage MIPS pipelined processor executing (i.e. fully completing) the given lines of code with forwarding wherever available as compared to a similar pipelined processor without forwarding (all dependencies handled with stalls)? Assume that the register file writes in the first half of the cycle and is read in the second half. Results written in the first half may be read in the second half. HINT: Complete the pipeline diagram (when forwarding is not available). Instruction 0 4 5 6 UHO 2 WP 8 add to $al, Sao H4 lw $t1 1024 ($t0) addi $to $50, 141 lw $t2 4096 ($t0) add $ti, $t2, $to