Design a $4-$bit shift register out of edge$-$triggered D$-$type$$NAND flip$-$flops.$$

The shift register has $4$ inputs and $4$ outputs$$for the data stored in the register $(4$ parallel lines to read$/$write$$the bit pattern in the register$).$ The outputs should be available$$continuously and should represent the current value stored in$$the register. The inputs should only be sampled $($and$$transferred into the register$)$ when an external load signal LD$$is high.$$

If the LD signal is low, then the shift register will perform$$either a left shift or a right shift on each clock pulse,$$depending on an external DIR signal. If DIR is low, the$$register shifts to the left $($toward the higher bit value$),$ if DIR is$$high$,$ the register shifts to the right $($toward the lower bit$$value$).$ A bit that would "shift out" is "shifted back in$"$ at the$$opposite end of the register. An example $($assuming LD and$$DIR are low!$)$ may make this clearer $($each arrow represents a$$clock pulse$)$:

$...-->0001-->0010-->0100-->1000-->0001-->...$

can you add diagrams and write in the student perspective please