Question: Design a 4 to 1 demultiplexer with 2 select inputs B and A, 4 data inputs (D3 to D0), and an output Y, You can

Design a 4 to 1 demultiplexer with 2 select inputs B and A,

4 data inputs (D3 to D0), and an output Y,

You can use just basic gates (AND, OR, NOT, NAND, NOR, XOR),

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