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Design a circuit for managing batches of rock - paper - scissors game. Two players enter a move, which can be paper, rock, or scissors.
Design a circuit for managing batches of rockpaperscissors game.
Two players enter a move, which can be paper, rock, or scissors. For each round, the player winning is decreed by the following rules:
Rock beats scissors;
Scissors beats paper;
Paper beats stone.
If the two players choose the same move, the round ends in a draw.
To make it more exciting, each game is divided into several rounds, with the following rules:
A minimum of four rounds must be played;
A maximum of nineteen rounds can be played. The maximum number of runs comes set to the clock cycle in which the game is started;
The first player to win two more rounds than his opponent wins, provided to have played at least four matches;
At each round, the winning player of the previous round cannot repeat the last one move used. If he did so the round would not be valid and would have to be repeated therefore not counted;
At each round, in case of a tie the round is counted. On to the next round, both players can use all moves.
The circuit has three inputs:
FIRST bit: move chosen by the first player. The moves have the following codes:
: no move;
: Stone;
: Card;
: Scissors;
SECOND bit: move chosen by the second player. The moves have the same codes as the first player.
START bit: when it is it returns the system to the initial configuration. Furthermore, the concatenation of FIRST and SECOND inputs is used to specify the maximum number of matches beyond the mandatory four. For example, if you entered the values FIRST and SECOND it would indicate playing exactly four games. If you entered the value FIRST and SECOND it would be indicated to play at most games the mandatory ones, plus the value indicated by If you entered the values FIRST and SECOND yes would indicate playing thirteen games the mandatory, plus the value indicated by
When it is the game continues normally.
The circuit has two outputs:
ROUND bit: provides the result of the last game played with the following coding:
: invalid run;
: round won by player ;
: round won by player ;
: heat tied.
MATCH bit: provides the result of the match with the following encoding:
: the game is not over;
: the game is over, and player has won;
: the game is over, and player has won;
: the match ended in a draw.
The circuit must be implemented in Verilog in the behavioral style and in SIS. The entrances and exits of the Verilog and SIS implementations must have the same order as above. The main module Verilog will have to be called RockPaperScissors. The Verilog testbench must generate, by printing the file called testbench.script, a script that acts as a testbench for the SIS model.
The Verilog model must generate a file, called outputverilog.txt that every clock cycle reports the outputs with the following format:
Outputs: ROUND ROUND MATCH MATCH
The report must explain in detail at least the following points:
a The general architecture of the circuit FSMD scheme;
b The state diagram of the controller;
c The datapath architecture;
d Circuit statistics before and after area optimization;
e The number of gates and delay obtained by mapping the design to the technology library synchgenlib;
f The description of any design choices made.
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